The present invention is related to simulating programmable processors, and in particular, to a method and apparatus for modifying a provided virtual processor model for use in simulating a target processor running target software in hardware/software simulation.
By a virtual processor model is meant a model, e.g., presented as a set of software instructions that when executing on a host processing system implement a method of simulating the functionality of a programmable hardware processor (“target processor,”) including simulating the timing and functionality of a set of target instructions (“target software”) for operating that target processor.
Systems on a chip (SoCs) that include programmable processors are in widespread use, and using a virtual processor model is particularly advantageous in designing such SoCs. The processor design is often obtained as a pre-defined core design for use in designing a SoC.
Virtual processor models are detailed and therefore not trivial to design from start. As a result, vendors such as VaST Systems Technology Corporation of Sunnyvale, Calif., the assignee of the present invention, provide pre-defined virtual processor models for many popular processors.
Many SoCs however are designed to include a custom processor, e.g., one that might be similar to an available processor design, but have different word lengths, different operations, and so forth. There is a need in the art to be able to simulate the operation of such a custom processor using a virtual processor model, but yet custom design of a virtual processor model might not be warranted. Some processor types, however, contain many structures in common. Furthermore, processors tend to fall into families that have aspects in common.
There is a need in the art for a customizable virtual processor model, and for a method and apparatus for modifying a provided virtual processor model.